This invention relates to a six-transistor or full CMOS (complementary metal-oxide-semiconductor) SRAM (static random access memory) cell.
In the manner which will later be exemplified in greater detail, various CMOS SRAM cells are already known and are used in full CMOS SRAM's. A general CMOS SRAM comprises a plurality of word lines and a plurality of pairs of complementary data or bit lines. For example, a 256-kb CMOS SRAM comprises thirty-two word lines and eight pairs of complementary data lines, or eight data line pairs. In a full CMOS SRAM, a great number of full CMOS SRAM cells are arranged in a matrix fashion and are connected to the word lines and to the data line pairs. Each full CMOS SRAM cell comprises two driver transistors, two load transistors, and two transfer or selector transistors. In each of such memory or storage cells, gate electrodes of the transfer transistors are used as one of the word lines. One ends of source and drain terminals of the transfer transistors are connected to complementary data lines of each pair, respectively.
In the full CMOS SRAM cell, other ends of the source and drain terminals are connected to first and second nodes. First and second inverters are composed of the driver and the load transistors. Gate electrodes of the driver and the load transistors of the first inverter are connected to the second node. Likewise, gate electrodes of the second inverter are connected to the first node. Source electrodes of the load transistors are connected to a power or Vcc bus. Source electrodes of the driver transistors are connected to a reference or ground or Vss bus. Drain electrodes of the driver and the load transistors of the first inverter are connected to each other at the first node. Similarly, drain electrodes are connected in the second inverter to each other at the second node.
A full CMOS SRAM cell is described in a paper which is contributed by Akinori Sekiyama and five others to the IEEE Journal of Solid-state Circuits, Volume 27, No. 5, May 1992, pages 776 to 782, under the title of "A 1-V Operating 256-kb Full-CMOS SRAM". Another full CMOS SRAM cell is disclosed in Japanese Patent Prepublication (A) No. 130,880 of 1995. Other full CMOS SRAM's are proposed in the 1996 Symposium on VLSI Technology held Jun. 11 to 13, 1996, jointly by the IEEE Electron Devices Society and the Japan Society of Applied Physics. For example, a Novel Local Interconnect Technology (MSD) for High-Performance Logic LSIs with Embedded SRAM was presented by T. Uehara and twelve others as Paper No. 15.1. A 5-.mu.m.sup.2 Full-CMOS Cell for High-Speed SRAMs Utilizing a [sic] Optical-Proximity-Effect Correction (OPC) Technology was presented by Masahiro Ueshima and eight others as Paper No. 15.3.
Such conventional full CMOS SRAM cells have a common equivalent circuit. Between these memory cells, differences reside in their layout patterns. According to conventional layout patterns, each memory cell is long along each of the complementary data line pair. More specifically, three transistors are arranged in each memory cell along each data line. As a consequence, each data line has a large parasitic capacitance. This makes it difficult to raise the speed of accessing each memory cell.
In addition, the complementary data lines of each pair are disposed parallel and adjacent to each other. When the memory cell is manufactured according to a fine design rule and put in operation with a low voltage, capacitive coupling becomes serious in the complementary data lines of each pair. As a result of noise between these complementary data line pair, operation of the CMOS SRAM becomes unstable.
Moreover, the power buses cross the complementary data lines and the reference buses in the CMOS SRAM of the Sekiyama et al paper. As for the Japanese patent prepublication, one of the complementary data lines of each pair or in the memory cells arranged along this data line and one of the complementary data lines of an adjacent pair or in adjacent memory cells aligned along this latter data line are disposed parallel and adjacent to each other to make it more difficult to avoid the capacitive coupling. In addition, the power buses are buried or embedded although the complementary data lines and the reference buses are on a single level. Moreover, a plurality of intracell connections are used on a different level in connecting the reference buses to the driver transistors.